Datasheet > 74LS161

74LS161

更新时间： 2024-01-09 06:58:25

品牌	Logo	应用领域
SLS		计数器逻辑集成电路光电二极管
页数	文件大小	规格书
5页	49K
描述
Synchronous 4 Bit Counters; Binary, Direct Reset

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74LS161 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP16,.3	Reach Compliance Code：	compliant
风险等级：	5.92	计数方向：	UP
JESD-30 代码：	R-PDIP-T16	JESD-609代码：	e0
负载/预设输入：	YES	逻辑集成电路类型：	BINARY COUNTER
工作模式：	SYNCHRONOUS	功能数量：	1
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP16,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
电源：	5 V	子类别：	Counters
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	TTL	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
Base Number Matches：	1

74LS161 数据手册

SL74LS161

Synchronous 4 Bit Counters; Binary,

Direct Reset

This synchronous, presettable counter features an internal carry

look-ahead for application in high-speed counting designs.

Synchronous operation is provided by having all flip-flops clocked

simultaneously so that the outputs change conicident with each other

when so instructed by the count-enable inputs and internal gating.

This mode of operation eliminates the output counting spikes that

are normally associated with asynchronous (ripple clock) counters. A

buffered clock input triggers the four flip-flops on the rising (positive-

going) edge of the clock input wave form.

This counter is fully programmable; that is the outputs may be

preset to either level. As presetting is synchronous setting up a low

level at the load input disables the counter and causes the outputs to

agree with the setup data after the next clock pulse regardless of the

levels of the enable inputs.

The carry look-ahead circuitry provides for cascading counters for

n-bit synchronous applications without additional gating. Instrumental

in accomplishiing this function are two counter-enable inputs and a

ripple carry output. Both countenable inputs (ENABLE P and

ENABLE T) must be high to count, and ENABLE T is fed forward to

enable the ripple carry output. The ripple carry output thus enabled

will produce a high-level output pulse with a duration approximately

ORDERING INFORMATION

SL74LS161N Plastic

SL74LS161D SOIC

T_A= 0° to 70° C for all

packages

PIN ASSIGNMENT

equal to the high level portion of the Q output. The high-level

overflow ripple carry pulse can be enable successive cascaded

stages. Transitions at the ENPor ENT are allowed regardless of the

level of the clock input.

Internal Look-Ahead for Fast Counting

Carry Output for n-Bit Cascading

Synchronous Counting

Synchronously Programmable

Load Control Line

Diode-Clamped Inputs

LOGIC DIAGRAM

PIN 16 =V_CC

PIN 8 = GND

System Logic

Semiconductor

SLS

12 3 4 5

中文翻译

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与74LS161相关器件

型号	品牌	获取价格	描述	数据表
74LS161ADC	ETC	获取价格	Synchronous Up Counter
74LS161APC	ETC	获取价格	Synchronous Up Counter
74LS161ASC	ETC	获取价格	Synchronous Up Counter
74LS161B	NXP	获取价格	IC LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16, PLASTIC, DIP-16
74LS161DC	ETC	获取价格	Synchronous Up Counter
74LS161F	NXP	获取价格	IC LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, Counter
74LS161NA+1	RAYTHEON	获取价格	Binary Counter, Synchronous, Up Direction, TTL, PDIP16,
74LS161PC	ETC	获取价格	Synchronous Up Counter
74LS162	TI	获取价格	SYNCHRONOUS 4-BIT COUNTERS
74LS162	MOTOROLA	获取价格	BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS

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