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74LS11

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74LS11 数据手册

August 1986

Revised March 2000

DM74LS11

Triple 3-Input AND Gate

General Description

This device contains three independent gates each of

which performs the logic AND function.

Ordering Code:

Order Number Package Number

Package Description

DM74LS11M

DM74LS11N

M14A

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Y = ABC

Inputs

Output

H = HIGH Logic Level

L = LOW Logic Level

X = Either LOW or HIGH Logic Level

DS006350

www.fairchildsemi.com

12 3 4

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型号	品牌	获取价格	描述	数据表
74LS112	TI	获取价格	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
74LS112	FAIRCHILD	获取价格	Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complement
74LS112	MOTOROLA	获取价格	DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
74LS112	HITACHI	获取价格	Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear)
74LS112B	NXP	获取价格	J-K Flip-Flop, LS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TT
74LS112DC	ETC	获取价格	J-K-Type Flip-Flop
74LS112DCQR	FAIRCHILD	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDIP16,
74LS112F	NXP	获取价格	IC LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, CE
74LS112N	RAYTHEON	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDIP16,
74LS112PC	ETC	获取价格	J-K-Type Flip-Flop