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74LS03SC PDF预览

74LS03SC

更新时间: 2024-02-29 03:12:09
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
4页 51K
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74LS03SC 数据手册

 浏览型号74LS03SC的Datasheet PDF文件第2页浏览型号74LS03SC的Datasheet PDF文件第3页浏览型号74LS03SC的Datasheet PDF文件第4页 
August 1986  
Revised March 2000  
DM74LS03  
Quad 2-Input NAND Gates with Open-Collector Outputs  
General Description  
Pull-Up Resistor Equations  
This device contains four independent gates each of which  
performs the logic NAND function. The open-collector out-  
puts require external pull-up resistors for proper logical  
operation.  
Where:  
N1 (IOH) = total maximum output high current  
for all outputs tied to pull-up resistor  
N2 (IIH) = total maximum input high current for  
all inputs tied to pull-up resistor  
N3 (IIL) = total maximum input low current for  
all inputs tied to pull-up resistor  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS03M  
DM74LS03N  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = AB  
Inputs  
Output  
A
L
B
L
Y
H
H
H
L
L
H
L
H
H
H
H = HIGH Logic Level  
L = LOW Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS006344  
www.fairchildsemi.com  

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