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74LS00 PDF预览

74LS00

更新时间: 2024-02-10 18:41:57
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
5页 63K
描述
Quad 2-Input NAND Gate

74LS00 技术参数

生命周期:Obsolete包装说明:SOP, SOP14,.25
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.42JESD-30 代码:R-PDSO-G14
逻辑集成电路类型:NAND GATE端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:5 V
认证状态:Not Qualified施密特触发器:NO
子类别:Gates标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

74LS00 数据手册

 浏览型号74LS00的Datasheet PDF文件第2页浏览型号74LS00的Datasheet PDF文件第3页浏览型号74LS00的Datasheet PDF文件第4页浏览型号74LS00的Datasheet PDF文件第5页 
August 1986  
Revised March 2000  
DM74LS00  
Quad 2-Input NAND Gate  
General Description  
This device contains four independent gates each of which  
performs the logic NAND function.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS00M  
DM74LS00SJ  
DM74LS00N  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = AB  
Inputs  
Output  
A
L
B
L
Y
H
H
H
L
L
H
L
H
H
H
H = HIGH Logic Level  
L = LOW Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS006439  
www.fairchildsemi.com  

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