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74LCXZ163245MTD PDF预览

74LCXZ163245MTD

更新时间: 2024-09-23 23:24:19
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其他 - ETC 总线收发器逻辑集成电路光电二极管
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7页 76K
描述
Dual 8-bit Bus Transceiver

74LCXZ163245MTD 数据手册

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Preliminary  
May 2001  
Revised May 2001  
74LCXZ163245  
16-Bit Dual Supply Translating Transceiver  
with 3-STATE Outputs (Preliminary)  
so that the control pins (T/Rn, OEn) are powered by VCCB  
,
General Description  
so that VCCA may be removed when the I/Os are disabled.  
The 74LCXZ163245 is a dual supply, 16-bit, translating  
transceiver that is designed for two-way asynchronous  
communication between busses at different supply volt-  
ages. This device is suited for PCMCIA and other real-time  
configurable I/O applications that utilize mixed power sup-  
plies.  
The 74LCXZ163245 is suitable for mixed voltage applica-  
tions such as notebook computers using a 3.3V CPU and  
5.0V peripheral components. It is fabricated with an  
Advanced CMOS technology to achieve high speed opera-  
tion while maintaining low CMOS power dissipation.  
The 74LCXZ163245 is designed to Power-Up and Power-  
Down into a High Impedance state (outputs disabled). The  
feature eliminates the need to power-up in a specific  
sequence to avoid drawing excessive current.  
Features  
Bidirectional interface between 3V busses and  
5V busses  
The A Port interfaces with the higher voltage bus (3.0V to  
5.5V), and the B Port interfaces with the lower voltage bus  
(2.3V to 3.6V). This dual supply design allows for transla-  
tion from low voltage busses (2.3V to 3.6V) to busses at a  
higher potential, up to 5.5V. The 74LCXZ163245 is  
intended to be used in applications where the A Port is con-  
nected to the PCMCIA card slots, and the B Port is con-  
nected to the 3.0V host system.  
Supports live insertion and withdrawal (Note 1)  
Outputs source/sink up to 24 mA  
Uses patented Quiet Series noise/EMI reduction  
circuitry  
Functionally compatible with the 74 series 16245  
Port A I/O may be disabled by use of OEn or removal of  
A Port VCC  
Furthermore, when both OE’s are HIGH, the A Port I/O pins  
are disabled, and both A Port I/O connections and A Port  
VCC are allowed to float. This feature permits PCMCIA  
Port A VCC may be removed when OEn is used to  
disable I/O’s  
Port A VCC removal may occur coincident with rising  
edge of OEn  
cards to be inserted and removed during normal operation.  
The Transmit/Receive (T/R) input determines the direction  
of data flow. Transmit (active-HIGH) enables data from A  
Ports to B Ports; Receive (active-LOW) enables data from  
B Ports to A Ports. The Output Enable (OE1, OE2) inputs,  
Configurable as one 16-bit or two 8-bit transceivers  
Unrestricted power-up sequencing  
Note 1: To ensure the high impedance state during power up or down OE  
when HIGH, disable their associated ports by placing the  
I/Os in HIGH-Z condition. The 74LCXZ163245 is designed  
should be tied to VCC through a pull-up resistor; the minimum value of the  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LCXZ163245MTD  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Quiet Series is a trademark of Fairchild Semiconductor Corporation.  
© 2001 Fairchild Semiconductor Corporation  
DS500364  
www.fairchildsemi.com  

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