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74LCX652 PDF预览

74LCX652

更新时间: 2024-11-16 22:56:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
10页 97K
描述
Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs

74LCX652 数据手册

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February 1994  
Revised April 1999  
74LCX652  
Low Voltage Transceiver/Register with 5V Tolerant  
Inputs and Outputs  
General Description  
Features  
5V tolerant inputs and outputs  
The LCX652 consists of bus transceiver circuits with D-  
type flip-flops, and control circuitry arranged for multiplexed  
transmission of data directly from the input bus or from  
internal registers. Data on the A or B bus will be clocked  
into the registers as the appropriate clock pin goes to the  
HIGH logic level. Output Enable pins (OEAB, OEBA) are  
provided to control the transceiver function.  
2.3V 3.6V VCC specifications provided  
7.0 ns tPD max (VCC = 3.3V), 10 µA ICC max  
Power down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
±24 mA output drive (VCC = 3.0V)  
The LCX652 is designed for low voltage (2.5V or 3.3V) VCC  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
applications with capability of interfacing to a 5V signal  
environment.  
The LCX652 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to V  
through a pull-up resistor: the minimum value or the  
CC  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX652WM  
74LCX652MSA  
74LCX652MTC  
M24B  
MSA24  
MTC24  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
A0–A7, B0–B7  
CPAB, CPBA  
SAB, SBA  
Description  
A and B Inputs/3-STATE Outputs  
Clock Inputs  
Select Inputs  
OEAB, OEBA  
Output Enable Inputs  
© 1999 Fairchild Semiconductor Corporation  
DS011998.prf  
www.fairchildsemi.com  

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