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74LCX652

更新时间: 2024-11-19 04:47:47
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意法半导体 - STMICROELECTRONICS 总线收发器输出元件输入元件
页数 文件大小 规格书
16页 391K
描述
LOW VOLT. CMOS OCTAL BUS TRANSCEIVER/REGISTER WITH 5 VOLT TOLERANT INPUTS AND OUTPUTS(3-STATE)

74LCX652 数据手册

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74LCX652  
LOW VOLT. CMOS OCTAL BUS TRANSCEIVER/REGISTER  
WITH 5 VOLT TOLERANT INPUTS AND OUTPUTS(3-STATE)  
5V TOLERANT INPUTS AND OUTPUTS  
HIGH SPEED:  
t
= 7.0 ns (MAX.) at V = 3V  
PD  
CC  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOP  
TSSOP  
T & R  
|I | = I = 24mA (MIN) at V = 3V  
OH  
OL  
CC  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
Table 1: Order Codes  
PACKAGE  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2.0V to 3.6V (1.5V Data  
SOP  
74LCX652RM13TR  
74LCX652TTR  
V
CC  
TSSOP  
Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 652  
This device consists of bus transceiver circuits  
with 3 state, D-type flip-flops, and control circuitry  
arranged for multiplexed transmission of data  
directly from the input bus or from the internal  
storage registers. Enable (GAB) and (GBA) pins  
are provided to control the transceiver functions.  
Select AB and Select BA control pins are provided  
to select whether real-time or stored data is  
transferred. A low input level selects real-time,  
and a high selects stored data.  
Data on the A or B bus, or both, can be stored in  
the internal D flip-flop by low to high transitions at  
the appropriate clock pins (CAB or CBA)  
regardless of the select or enable control pins.  
When select AB and select BA are in the real-time  
transfer mode, it is also possible to store data  
LATCH-UP PERFORMANCE EXCEEDS  
500mA (JESD 17)  
ESD PERFORMANCE:  
HBM > 2000V (MIL STD 883 method 3015);  
MM > 200V  
DESCRIPTION  
The 74LCX652 is a low voltage CMOS OCTAL  
BUS  
(3-STATE) fabricated with sub-micron silicon gate  
and double-layer metal wiring C MOS technology.  
It is ideal for low power and high speed 3.3V  
applications; it can be interfaced to 5V signal  
environment for both inputs and outputs.  
TRANSCEIVER  
AND  
REGISTER  
2
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 6  
1/16  
September 2004  

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