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74LCX573SJ PDF预览

74LCX573SJ

更新时间: 2024-11-03 22:56:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 555K
描述
Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs

74LCX573SJ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOP
包装说明:SOP, SOP20,.3针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.1
其他特性:BROADSIDE VERSION OF 373系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.6 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:RAIL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:8 ns
传播延迟(tpd):10.5 ns认证状态:Not Qualified
座面最大高度:2.1 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:5.3 mm
Base Number Matches:1

74LCX573SJ 数据手册

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March 1995  
Revised March 2005  
74LCX573  
Low Voltage Octal Latch with 5V Tolerant  
Inputs and Outputs  
General Description  
The LCX573 is a high-speed octal latch with buffered com-  
mon Latch Enable (LE) and buffered common Output  
Enable (OE) inputs.  
Features  
5V tolerant inputs and outputs  
2.3V–3.6V VCC specifications provided  
7.0 ns tPD max (VCC 3.3V), 10 A ICC max  
The LCX573 is functionally identical to the LCX373 but has  
inputs and outputs on opposite sides.  
Power down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
The LCX573 is designed for low voltage (3.3V or 2.5V)  
applications with capability of interfacing to a 5V signal  
environment. The LCX573 is fabricated with an advanced  
CMOS technology to achieve high speed operation while  
maintaining CMOS low power dissipation.  
24 mA output drive (VCC 3.0V)  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds JEDEC 78 conditions  
ESD performance:  
Human body model 2000V  
Machine model 200V  
Leadless Pb-Free DQFN package  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to V  
through a pull-up resistor: the minimum value or the  
CC  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LCX573WM  
74LCX573SJ  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LCX573BQX  
(Preliminary)  
(Note 2)  
MLP020B Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC  
MO-241, 2.5 x 4.5mm  
74LCX573MSA  
74LCX573MTC  
MSA20  
MTC20  
MTC20  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LCX573MTCX_NL  
(Note 3)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 2: DQFN package available in Tape and Reel only.  
Note 3: _NLindicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
© 2005 Fairchild Semiconductor Corporation  
DS012405  
www.fairchildsemi.com  

74LCX573SJ 替代型号

型号 品牌 替代类型 描述 数据表
74LCX573SJX FAIRCHILD

完全替代

Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs
MC74LCX573MEL ONSEMI

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Low-Voltage CMOS Octal Transparent Latch Flow Through Pinout With 5 V−Tolerant Input
MC74LCX573M ONSEMI

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LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH

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