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74LCX543MSAX PDF预览

74LCX543MSAX

更新时间: 2024-11-17 23:24:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线收发器
页数 文件大小 规格书
8页 93K
描述
Single 8-bit Bus Transceiver

74LCX543MSAX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP24,.3
针数:24Reach Compliance Code:compliant
风险等级:5.35其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G24
JESD-609代码:e3长度:8.2 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP24,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:7 ns传播延迟(tpd):10.5 ns
认证状态:Not Qualified座面最大高度:2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:5.3 mm
Base Number Matches:1

74LCX543MSAX 数据手册

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May 1995  
Revised March 2001  
74LCX543  
Low Voltage Octal Registered Transceiver with  
5V Tolerant Inputs and Outputs  
General Description  
Features  
5V tolerant inputs and outputs  
The LCX543 is a non-inverting octal transceiver containing  
two sets of D-type registers for temporary storage of data  
flowing in either direction. Separate Latch Enable and Out-  
put Enable inputs are provided for each register to permit  
independent input and output control in either direction of  
data flow.  
2.3V 3.6V VCC specifications provided  
7.0 ns tPD max (VCC = 3.3V), 10 µA ICC max  
Power down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
±24 mA Output Drive (VCC = 3.0V)  
The LCX543 is designed for low voltage (2.5V or 3.3V) VCC  
applications with capability of interfacing to a 5V signal  
environment.  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
The LCX543 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to VCC through a pull-up resistor: the minimum value or the  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX543WM  
74LCX543MSA  
74LCX543MTC  
M24B  
MSA24  
MTC24  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
OEAB  
OEBA  
CEAB  
CEBA  
LEAB  
LEBA  
A0A7  
A-to-B Output Enable Input (Active LOW)  
B-to-A Output Enable Input (Active LOW)  
A-to-B Enable Input (Active LOW)  
B-to-A Enable Input (Active LOW)  
A-to-B Latch Enable Input (Active LOW)  
B-to-A Latch Enable Input (Active LOW)  
A-to-B Data Inputs or  
B-to-A 3-STATE Outputs  
B0B7  
B-to-A Data Inputs or  
A-to-B 3-STATE Outputs  
© 2001 Fairchild Semiconductor Corporation  
DS012463  
www.fairchildsemi.com  

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