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74LCX543CW PDF预览

74LCX543CW

更新时间: 2024-11-09 20:11:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 逻辑集成电路
页数 文件大小 规格书
8页 78K
描述
Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 8-Bit, True Output, CMOS

74LCX543CW 技术参数

生命周期:Obsolete包装说明:DIE,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.68系列:LVC/LCX/Z
JESD-30 代码:X-XUUC-N24逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:UNSPECIFIED封装形式:UNCASED CHIP
传播延迟(tpd):10.5 ns认证状态:Not Qualified
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:NO LEAD
端子位置:UPPERBase Number Matches:1

74LCX543CW 数据手册

 浏览型号74LCX543CW的Datasheet PDF文件第2页浏览型号74LCX543CW的Datasheet PDF文件第3页浏览型号74LCX543CW的Datasheet PDF文件第4页浏览型号74LCX543CW的Datasheet PDF文件第5页浏览型号74LCX543CW的Datasheet PDF文件第6页浏览型号74LCX543CW的Datasheet PDF文件第7页 
May 1995  
Revised April 1999  
74LCX543  
Low Voltage Octal Registered Transceiver with  
5V Tolerant Inputs and Outputs  
General Description  
Features  
5V tolerant inputs and outputs  
The LCX543 is a non-inverting octal transceiver containing  
two sets of D-type registers for temporary storage of data  
flowing in either direction. Separate Latch Enable and Out-  
put Enable inputs are provided for each register to permit  
independent input and output control in either direction of  
data flow.  
2.3V 3.6V VCC specifications provided  
7.0 ns tPD max (VCC = 3.3V), 10 µA ICC max  
Power down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
±24 mA Output Drive (VCC = 3.0V)  
The LCX543 is designed for low voltage (2.5V or 3.3V) VCC  
applications with capability of interfacing to a 5V signal  
environment.  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
The LCX543 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to V  
through a pull-up resistor: the minimum value or the  
CC  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX543WM  
74LCX543MSA  
74LCX543MTC  
M24B  
MSA24  
MTC24  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
OEAB  
OEBA  
CEAB  
Description  
A-to-B Output Enable Input (Active LOW)  
B-to-A Output Enable Input (Active LOW)  
A-to-B Enable Input (Active LOW)  
B-to-A Enable Input (Active LOW)  
A-to-B Latch Enable Input (Active LOW)  
B-to-A Latch Enable Input (Active LOW)  
A-to-B Data Inputs or  
CEBA  
LEAB  
LEBA  
A0–A7  
B-to-A 3-STATE Outputs  
B0–B7  
B-to-A Data Inputs or  
A-to-B 3-STATE Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS012463.prf  
www.fairchildsemi.com  

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