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74LCX543 PDF预览

74LCX543

更新时间: 2024-11-17 22:56:19
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飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
8页 93K
描述
Low Voltage Octal Registered Transceiver with 5V Tolerant Inputs and Outputs

74LCX543 数据手册

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May 1995  
Revised March 2001  
74LCX543  
Low Voltage Octal Registered Transceiver with  
5V Tolerant Inputs and Outputs  
General Description  
Features  
5V tolerant inputs and outputs  
The LCX543 is a non-inverting octal transceiver containing  
two sets of D-type registers for temporary storage of data  
flowing in either direction. Separate Latch Enable and Out-  
put Enable inputs are provided for each register to permit  
independent input and output control in either direction of  
data flow.  
2.3V 3.6V VCC specifications provided  
7.0 ns tPD max (VCC = 3.3V), 10 µA ICC max  
Power down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
±24 mA Output Drive (VCC = 3.0V)  
The LCX543 is designed for low voltage (2.5V or 3.3V) VCC  
applications with capability of interfacing to a 5V signal  
environment.  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
The LCX543 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to VCC through a pull-up resistor: the minimum value or the  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX543WM  
74LCX543MSA  
74LCX543MTC  
M24B  
MSA24  
MTC24  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
OEAB  
OEBA  
CEAB  
CEBA  
LEAB  
LEBA  
A0A7  
A-to-B Output Enable Input (Active LOW)  
B-to-A Output Enable Input (Active LOW)  
A-to-B Enable Input (Active LOW)  
B-to-A Enable Input (Active LOW)  
A-to-B Latch Enable Input (Active LOW)  
B-to-A Latch Enable Input (Active LOW)  
A-to-B Data Inputs or  
B-to-A 3-STATE Outputs  
B0B7  
B-to-A Data Inputs or  
A-to-B 3-STATE Outputs  
© 2001 Fairchild Semiconductor Corporation  
DS012463  
www.fairchildsemi.com  

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