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74LCX541MSAX PDF预览

74LCX541MSAX

更新时间: 2024-11-17 23:24:19
品牌 Logo 应用领域
其他 - ETC 驱动器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
10页 101K
描述
8-Bit Non-Inverting Buffer/Driver

74LCX541MSAX 数据手册

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March 1995  
Revised March 2001  
74LCX541  
Low Voltage Octal Buffer/Line Driver  
with 5V Tolerant Inputs and Outputs  
General Description  
Features  
5V tolerant input and outputs  
The LCX541 is an octal buffer/line driver designed to be  
employed as memory and address drivers, clock drivers  
and bus oriented transmitter/receivers. The LCX541 is a  
non inverting option of the LCX540.  
2.3V–3.6V VCC specifications provided  
6.5 ns tPD max (VCC = 3.3V), 10 µA ICC max  
Power-down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
±24 mA output drive (VCC = 3.0V)  
This device is similar in function to the LCX244 while pro-  
viding flow-through architecture (inputs on opposite side  
from outputs). This pinout arrangement makes this device  
especially useful as an output port for microprocessors,  
allowing ease of layout and greater PC board density.  
Implements patented noise/ EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
The LCX541 is designed for low voltage (2.5V or 3.3V) VCC  
applications with capability of interfacing to a 5V signal  
environment. The LCX541 is fabricated with an advanced  
CMOS technology to achieve high speed operation while  
maintaining CMOS low power dissipation.  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or down,  
OE should be tied to VCC through a pull-up resistor: the minimum value  
or the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX541WM  
74LCX541SJ  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LCX541MSA  
74LCX541MTC  
MSA20  
MTC20  
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
© 2001 Fairchild Semiconductor Corporation  
DS012404  
www.fairchildsemi.com  

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