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74LCX273WMX PDF预览

74LCX273WMX

更新时间: 2024-11-19 21:53:55
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
2页 66K
描述
Low-Voltage Octal D Flip-Flop with 5V Tolerant Inputs and Outputs

74LCX273WMX 数据手册

 浏览型号74LCX273WMX的Datasheet PDF文件第2页 
ADVANCE INFORMATION  
November 1996  
74LCX273  
Low-Voltage Octal D Flip-Flop  
with 5V Tolerant Inputs and Outputs  
General Description  
Features  
Y
5V tolerant inputs and outputs  
The LCX273 has eight edge-triggered D-type flip-flops with  
individual D inputs and Q outputs. The common buffered  
Clock (CP) and Master Reset (MR) input load and reset  
(clear) all flip-flops simultaneously.  
Y
Y
Y
Y
Y
Y
10 mA I  
max  
CCQ  
Power-down high impedance inputs and outputs  
Supports live insertion/withdrawal  
The register is fully edge-triggered. The state of each D in-  
put, one setup time before the LOW-to-HIGH clock tran-  
sition, is transferred to the corresponding flip-flop’s Q out-  
put.  
2.0V3.6V V supply operation  
24 mA output drive  
CC  
g
Implements patented Quiet SeriesTM noise/EMI  
reduction circuitry  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The  
device is useful for applications where the true output only is  
required and the Clock and Master Reset are common to all  
storage elements.  
Y
Y
Y
Functionally compatible with the 74 series 273  
Latch-up performance exceeds 500 mA  
ESD performance:  
l
200V  
Human Body Model  
l
2000V  
Machine Model  
The device is designed for low voltage (3.3V) V  
applica-  
CC  
tions with capability of interfacing to a 5V signal environ-  
ment. The LCX273 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing CMOS low power dissipation.  
Logic Symbols  
Connection Diagram  
Pin Assignment for  
SOIC, SSOP and TSSOP  
IEEE/IEC  
TL/F/12640–1  
TL/F/12640–3  
TL/F/12640–2  
Pin Names  
Description  
D D  
0
Data Inputs  
7
MR  
CP  
Master Reset  
Clock Pulse Input  
Data Outputs  
Q Q  
0
7
SOIC JEDEC  
SOIC EIAJ  
SSOP Type II  
TSSOP JEDEC  
Order Number  
74LCX273WM  
74LCX273WMX  
74LCX273SJ  
74LCX273MSA  
74LCX273MSAX  
74LCX273MTC  
74LCX273MTCX  
74LCX273SJX  
See NS Package Number  
M20B  
M20D  
MSA20  
MTC20  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
Quiet SeriesTM is a trademark of National Semiconductor Corporation.  
C
1996 National Semiconductor Corporation  
TL/F/12640  
RRD-B30M17/Printed in U. S. A.  
http://www.national.com  

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