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74LCX241MSA PDF预览

74LCX241MSA

更新时间: 2024-11-25 22:45:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
10页 118K
描述
Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs

74LCX241MSA 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP20,.3
针数:20Reach Compliance Code:compliant
风险等级:5.63其他特性:OUTPUT ENABLE ACTIVE HIGH FOR ONE FUNCTION
控制类型:ENABLE LOW/HIGH系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:7.2 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:RAIL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:6.5 ns传播延迟(tpd):7.8 ns
认证状态:Not Qualified座面最大高度:2.05 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

74LCX241MSA 数据手册

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August 1998  
Revised March 2005  
74LCX241  
Low Voltage Octal Buffer/Line Driver with  
5V Tolerant Inputs and Outputs  
General Description  
Features  
5V tolerant inputs and outputs  
The LCX241 is an octal buffer and line driver designed to  
be employed as a memory address driver, clock driver and  
bus oriented transmitter or receiver. The device is designed  
for low voltage (2.5V or 3.3V) VCC applications with capa-  
2.3V – 3.6V VCC specifications provided  
6.5 ns tPD max (VCC 3.3V), 10 A ICC max  
Power-down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
bility of interfacing to a 5V signal environment.  
The LCX241 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Human Body Model 2000V  
Machine Model 200V  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to V and OE should be tied to GND through a resistor: the  
CC  
minimum value or the resistor is determined by the current-sourcing capa-  
bility of the driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX241WM  
74LCX241SJ  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LCX241MSA  
74LCX241MTC  
MSA20  
MTC20  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
OE1, OE2  
I0I7  
3-STATE Output Enable Inputs  
Inputs  
O0O7  
Outputs  
© 2005 Fairchild Semiconductor Corporation  
DS012639  
www.fairchildsemi.com  

74LCX241MSA 替代型号

型号 品牌 替代类型 描述 数据表
74LCX241WM FAIRCHILD

完全替代

Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
74LCX241WMX FAIRCHILD

完全替代

Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
74LCX241MSAX FAIRCHILD

完全替代

Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs

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