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74LCX240 PDF预览

74LCX240

更新时间: 2024-11-03 22:45:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件输入元件
页数 文件大小 规格书
9页 181K
描述
LOW VOLTAGE CMOS OCTAL BUS BUFFER (3-STATE INV) WITH 5V TOLERANT INPUTS AND OUTPUTS

74LCX240 数据手册

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74LCX240  
LOW VOLTAGE CMOS OCTAL BUS BUFFER (3-STATE INV.)  
WITH 5V TOLERANT INPUTS AND OUTPUTS  
5V TOLERANT INPUTS AND OUTPUTS  
HIGH SPEED :  
t
= 6.5 ns (MAX.) at V = 3V  
PD  
CC  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOP  
TSSOP  
|I | = I = 24mA (MIN) at V = 3V  
OH  
OL  
CC  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
t
t
PHL  
ORDER CODES  
PACKAGE  
PLH  
OPERATING VOLTAGE RANGE:  
(OPR) = 2.0V to 3.6V (1.5V Data  
TUBE  
T & R  
V
CC  
SOP  
74LCX240M  
74LCX240MTR  
74LCX240TTR  
Retention)  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 240  
LATCH-UP PERFORMANCE EXCEEDS  
500mA (JESD 17)  
ESD PERFORMANCE:  
HBM > 2000V (MIL STD 883 method 3015);  
MM > 200V  
speed 3.3V applications; it can be interfaced to 5V  
signal environment for both inputs and outputs.  
It has same speed performance at 3.3V than 5V  
AC/ACT family, combined with a lower power  
consumption.  
This device is designed to be used with 3 state  
memory address drivers, etc.  
DESCRIPTION  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
The 74LCX240 is a low voltage CMOS OCTAL  
BUS BUFFER fabricated with sub-micron silicon  
gate and double-layer metal wiring C MOS  
2
technology. It is ideal for low power and high  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
September 2001  
1/9  

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