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74LCX16841 PDF预览

74LCX16841

更新时间: 2024-11-03 22:45:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
8页 93K
描述
Low Voltage 20-Bit Transparent Latch with 5V Tolerant Inputs and Outputs

74LCX16841 数据手册

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October 1995  
Revised April 2001  
74LCX16841  
Low Voltage 20-Bit Transparent Latch  
with 5V Tolerant Inputs and Outputs  
General Description  
Features  
5V tolerant inputs and outputs  
The LCX16841 contains twenty non-inverting latches with  
3-STATE outputs and is intended for bus oriented applica-  
tions. The device is byte controlled. The flip-flops appear  
transparent to the data when the Latch Enable (LE) is  
HIGH. When LE is LOW, the data that meets the setup time  
is latched. Data appears on the bus when the Output  
Enable (OE) is LOW. When OE is HIGH, the outputs are in  
a high impedance state.  
2.3V–3.6V VCC specifications provided  
5.5 ns tPD max (VCC = 3.3V), 20 µA ICC max  
Power down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
±24 mA output drive (VCC = 3.0V)  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
The LCX16841 is designed for low voltage (2.5V or 3.3V)  
VCC applications with capability of interfacing to a 5V signal  
environment.  
Human body model > 2000V  
The LCX16841 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to VCC through a pull-up resistor: the minimum value or the  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX16841MEA  
74LCX16841MTD  
MS56A  
MTD56  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
OEn  
Description  
Output Enable Input (Active LOW)  
LEn  
Latch Enable Input  
Inputs  
D0D19  
O0O19  
Outputs  
© 2001 Fairchild Semiconductor Corporation  
DS012578  
www.fairchildsemi.com  

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