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74LCX16821MEA PDF预览

74LCX16821MEA

更新时间: 2024-11-03 22:45:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 83K
描述
Low Voltage 20-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

74LCX16821MEA 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:0.300 INCH, MO-118, SSOP-56针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.49
Is Samacsys:N系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G56JESD-609代码:e3
长度:18.415 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:150000000 Hz
最大I(ol):0.024 A湿度敏感等级:1
位数:10功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:RAIL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:6.2 ns传播延迟(tpd):7.4 ns
认证状态:Not Qualified座面最大高度:2.74 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.5 mm
Base Number Matches:1

74LCX16821MEA 数据手册

 浏览型号74LCX16821MEA的Datasheet PDF文件第2页浏览型号74LCX16821MEA的Datasheet PDF文件第3页浏览型号74LCX16821MEA的Datasheet PDF文件第4页浏览型号74LCX16821MEA的Datasheet PDF文件第5页浏览型号74LCX16821MEA的Datasheet PDF文件第6页浏览型号74LCX16821MEA的Datasheet PDF文件第7页 
January 1996  
Revised April 1999  
74LCX16821  
Low Voltage 20-Bit D-Type Flip-Flop with 5V Tolerant  
Inputs and Outputs  
General Description  
Features  
5V tolerant inputs and outputs  
The LCX16821 contains twenty non-inverting D-type flip-  
flops with 3-STATE outputs and is intended for bus oriented  
applications. The device is designed for low voltage (2.5V  
or 3.3V) VCC applications with capability of interfacing to a  
2.3V–3.6V VCC specifications provided  
6.2 ns tPD max (VCC = 3.3V), 20 µA ICC max  
Power down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
±24 mA output drive (VCC = 3.0V)  
5V signal environment.  
The LCX16821 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to V  
through a pull-up resistor: the minimum value or the  
CC  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX16821MEA  
MS56A  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LCX16821MTD  
MTD56  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
OEn  
Description  
Output Enable Input (Active LOW)  
Clock Input  
CLKn  
D0–D19  
O0–O19  
Inputs  
Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS012634.prf  
www.fairchildsemi.com  

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