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74LCX16652 PDF预览

74LCX16652

更新时间: 2024-09-12 22:45:59
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飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
10页 96K
描述
Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs

74LCX16652 数据手册

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February 1994  
Revised April 1999  
74LCX16652  
Low Voltage Transceiver/Register with 5V Tolerant  
Inputs and Outputs  
General Description  
Features  
5V tolerant inputs and outputs  
The LCX16652 contains sixteen non-inverting bidirectional  
bus transceivers with 3-STATE outputs providing multi-  
plexed transmission of data directly from the input bus or  
from the internal registers. Data on the A or B bus will be  
clocked into the registers as the appropriate clock pin goes  
to the HIGH logic level. Output Enable pins (OEAB, OEBA)  
are provided to control the transceiver function (see Func-  
tional Description).  
2.3V–3.6V VCC specifications provided  
5.7 ns tPD max (VCC = 3.3V), 20 µA ICC max  
Power down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
±24 mA output drive (VCC = 3.0V)  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
The LCX16652 is designed for low-voltage (2.5V or 3.3V)  
VCC applications with capability of interfacing to a 5V signal  
environment.  
Human body model > 2000V  
The LCX16652 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to V and OE tied to GND through a resistor: the minimum  
CC  
value or the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX16652MEA  
MS56A  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LCX16652MTD  
MTD56  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
A0–A15  
B0–B15  
Description  
Data Register A Inputs/3-STATE Outputs  
Data Register B Inputs/3-STATE Outputs  
CPABn, CPBAn Clock Pulse Inputs  
SABn, SBAn Select Inputs  
OEABn, OEBAn Output Enable Inputs  
© 1999 Fairchild Semiconductor Corporation  
DS012005.prf  
www.fairchildsemi.com  

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