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74LCX16240 PDF预览

74LCX16240

更新时间: 2024-11-23 22:45:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
8页 73K
描述
Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs

74LCX16240 数据手册

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February 1994  
Revised April 1999  
74LCX16240  
Low Voltage 16-Bit Inverting Buffer/Line Driver with  
5V Tolerant Inputs/Outputs  
General Description  
Features  
5V tolerant inputs and outputs  
The LCX16240 contains sixteen inverting buffers with 3-  
STATE outputs designed to be employed as a memory and  
address driver, clock driver, or bus-oriented transmitter/  
receiver. The device is nibble controlled. Each nibble has  
separate 3-STATE control inputs which can be shorted  
together for full 16-bit operation.  
2.3V–3.6V VCC specifications provided  
4.5 ns tPD max (VCC = 3.3V), 20 µA ICC max  
Power down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
±24 mA output drive (VCC = 3.0V)  
The LCX16240 is designed for low voltage (2.5V or 3.3V)  
VCC applications with capacity of interfacing to a 5V signal  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
environment.  
The LCX16240 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to V through a pull-up resistor: the minimum value or the  
CC  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX16240MEA  
MS48A  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LCX16240MTD  
MTD48  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OEn  
Output Enable Inputs (Active LOW)  
I0–I15  
O0–O15  
Inputs  
Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS011999.prf  
www.fairchildsemi.com  

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