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74LCX10MTCX_NL PDF预览

74LCX10MTCX_NL

更新时间: 2024-11-04 13:04:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
8页 109K
描述
NAND Gate, LVC/LCX/Z Series, 3-Func, 3-Input, CMOS, PDSO14, 4.40 MM, LEAD FREE, MO-153, TSSOP-14

74LCX10MTCX_NL 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.61系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G14JESD-609代码:e3/e4
长度:5 mm逻辑集成电路类型:NAND GATE
功能数量:3输入次数:3
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):5.9 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN/NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

74LCX10MTCX_NL 数据手册

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June 2000  
Revised February 2005  
74LCX10  
Low Voltage Triple 3-Input NAND Gate  
with 5V Tolerant Inputs  
General Description  
The LCX10 contains three 3-input NAND gates. The inputs  
tolerate voltages up to 7V allowing the interface of 5V sys-  
tems to 3V systems.  
Features  
5V tolerant inputs  
2.3V–3.6V VCC specifications provided  
4.9 ns tPD max (VCC 3.3V), 10 A ICC max  
Power down high impedance inputs and outputs  
The 74LCX10 is fabricated with advanced CMOS technol-  
ogy to achieve high speed operation while maintaining  
CMOS low power dissipation.  
24 mA output drive (VCC 3.0V)  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
Human body model 2000V  
Machine model 200V  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX10M  
M14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LCX10SJ  
74LCX10MTC  
MTC14  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Truth Table  
On An Bn Cn  
Pin Names  
An, Bn, Cn  
On  
Description  
Inputs  
An  
Bn  
Cn  
On  
Outputs  
X
X
L
X
L
L
X
X
H
H
H
H
L
X
H
H
H
L
HIGH Voltage Level  
LOW Voltage Level  
X
Immaterial  
© 2005 Fairchild Semiconductor Corporation  
DS500453  
www.fairchildsemi.com  

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