Datasheet > 74LCX07SJX

74LCX07SJX

更新时间： 2024-11-04 23:24:19

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
7页	80K
描述
Hex Buffer

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数据手册

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74LCX07SJX 数据手册

October 1999

Revised July 2001

74LCX07

Low Voltage Hex Buffer with Open Drain Outputs

General Description

The LCX07 contains six buffers. The inputs tolerate volt-

ages up to 7V allowing the interface of 5V systems to 3V

systems.

Features

■ 5V tolerant inputs

■ 2.3V–5.5V V_CCspecifications provided

■ 2.9 ns t_PDmax (V_CC= 3.3V), 10 µA I_CCmax

The outputs of the LCX07 are open drain and can be con-

nected to other open drain outputs to implement active

HIGH wire AND or active LOW wire OR functions.

■ Power down high impedance inputs and outputs

■ +24 mA output drive (V_CC= 3.0V)

The 74LCX07 is fabricated with advanced CMOS technol-

ogy to achieve high speed operation while maintaining

CMOS low power dissipation.

■ Implements patented noise/EMI reduction circuitry

■ Latch-up performance exceeds 500 mA

■ ESD performance:

Human body model > 2000V

Machine model > 200V

Ordering Code:

Order Number Package Number

Package Description

74LCX07M

M14A

M14D

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX07SJ

74LCX07MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names

Description

Inputs

Outputs

A_n

O_n

DS500238

www.fairchildsemi.com

12 3 4 5 6 7

中文翻译

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