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74LCX06SJ PDF预览

74LCX06SJ

更新时间: 2024-11-23 22:45:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
7页 95K
描述
Low Voltage Hex Inverter/Buffer with Open Drain Outputs

74LCX06SJ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOP
包装说明:SOP, SOP14,.3针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.32
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:10.2 mm
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
最大I(ol):0.024 A湿度敏感等级:1
功能数量:6输入次数:1
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出特性:OPEN-DRAIN
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:RAIL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:3.7 ns传播延迟(tpd):4.1 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2.1 mm子类别:Gates
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:5.3 mm

74LCX06SJ 数据手册

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October 1999  
Revised February 2005  
74LCX06  
Low Voltage Hex Inverter/Buffer with Open Drain Outputs  
General Description  
The LCX06 contains six inverters/buffers. The inputs toler-  
ate voltages up to 7V allowing the interface of 5V systems  
to 3V systems.  
Features  
5V tolerant inputs  
2.3V–3.6V VCC specifications provided  
3.7 ns tPD max (VCC 3.3V), 10 A ICC max  
The outputs of the LCX06 are open drain and can be con-  
nected to other open drain outputs to implement active  
LOW wire AND or active HIGH wire OR functions.  
Power down high impedance inputs and outputs  
24 mA output drive (VCC 3.0V)  
The 74LCX06 is fabricated with advanced CMOS technol-  
ogy to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
Functionally compatible with 74 series 05  
ESD performance:  
Human body model 2000V  
Machine model 200V  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LCX06M  
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74LCX06MX_NL  
(Note 1)  
74LCX06SJ  
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LCX06MTC  
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LCX06MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
(Note 1)  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: _NLindicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
Inputs  
An  
On  
Outputs  
© 2005 Fairchild Semiconductor Corporation  
DS500237  
www.fairchildsemi.com  

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