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74LCX02SJX PDF预览

74LCX02SJX

更新时间: 2024-11-04 03:56:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 91K
描述
Low Voltage Quad 2-Input NOR Gate with 5V Tolerant Inputs

74LCX02SJX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOP
包装说明:5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-14针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:6.89
Is Samacsys:N系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:10.2 mm负载电容(CL):50 pF
逻辑集成电路类型:NOR GATE最大I(ol):0.024 A
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:5.2 ns传播延迟(tpd):6.2 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2.1 mm子类别:Gates
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

74LCX02SJX 数据手册

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March 1995  
Revised January 2005  
74LCX02  
Low Voltage Quad 2-Input NOR Gate  
with 5V Tolerant Inputs  
General Description  
The LCX02 contains four 2-input NOR gates. The inputs  
tolerate voltages up to 7V allowing the interface of 5V sys-  
tems to 3V systems.  
Features  
5V tolerant inputs  
2.3V–3.6V VCC specification provided  
5.2 ns tPD max (VCC = 3.3V), 10 µA ICC max  
The 74LCX02 is fabricated with advanced CMOS technol-  
ogy to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Power down high impedance inputs and outputs  
±24 mA output drive (VCC = 3.0V)  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
Human body model > 2000V  
Machine model > 200V  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LCX02M  
M14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LCX02SJ  
74LCX02MTC  
MTC14  
MTC14  
74LCX02MTCX_NL  
(Note 1)  
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,  
4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: _NLpackage available in Tape and Reel only.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
An, Bn  
On  
Description  
Inputs  
Outputs  
© 2005 Fairchild Semiconductor Corporation  
ds012409  
www.fairchildsemi.com  

74LCX02SJX 替代型号

型号 品牌 替代类型 描述 数据表
74LCX02SJ FAIRCHILD

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Low Voltage Quad 2-Input NOR Gate
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