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74LCX02MTCX_NLX

更新时间： 2024-02-13 21:00:47

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		栅
页数	文件大小	规格书
8页	91K
描述
Low Voltage Quad 2-Input NOR Gate with 5V Tolerant Inputs

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数据手册

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74LCX02MTCX_NLX 数据手册

March 1995

Revised January 2005

74LCX02

Low Voltage Quad 2-Input NOR Gate

with 5V Tolerant Inputs

General Description

The LCX02 contains four 2-input NOR gates. The inputs

tolerate voltages up to 7V allowing the interface of 5V sys-

tems to 3V systems.

Features

■ 5V tolerant inputs

■ 2.3V–3.6V V_CCspecification provided

■ 5.2 ns t_PDmax (V_CC= 3.3V), 10 µA I_CCmax

The 74LCX02 is fabricated with advanced CMOS technol-

ogy to achieve high speed operation while maintaining

CMOS low power dissipation.

■ Power down high impedance inputs and outputs

■ ±24 mA output drive (V_CC= 3.0V)

■ Implements patented noise/EMI reduction circuitry

■ Latch-up performance exceeds 500 mA

■ ESD performance:

Human body model > 2000V

Machine model > 200V

Ordering Code:

Package

Order Number

Package Description

Number

74LCX02M

M14A

M14D

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74LCX02SJ

74LCX02MTC

MTC14

74LCX02MTCX_NL

(Note 1)

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” package available in Tape and Reel only.

Logic Symbol

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names

A_n, B_n

O_n

Description

Inputs

Outputs

ds012409

www.fairchildsemi.com

12 3 4 5 6 7 8

中文翻译

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