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74LCX02MTCX_NLX PDF预览

74LCX02MTCX_NLX

更新时间: 2024-11-04 04:47:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
8页 91K
描述
Low Voltage Quad 2-Input NOR Gate with 5V Tolerant Inputs

74LCX02MTCX_NLX 数据手册

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March 1995  
Revised January 2005  
74LCX02  
Low Voltage Quad 2-Input NOR Gate  
with 5V Tolerant Inputs  
General Description  
The LCX02 contains four 2-input NOR gates. The inputs  
tolerate voltages up to 7V allowing the interface of 5V sys-  
tems to 3V systems.  
Features  
5V tolerant inputs  
2.3V–3.6V VCC specification provided  
5.2 ns tPD max (VCC = 3.3V), 10 µA ICC max  
The 74LCX02 is fabricated with advanced CMOS technol-  
ogy to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Power down high impedance inputs and outputs  
±24 mA output drive (VCC = 3.0V)  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
Human body model > 2000V  
Machine model > 200V  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LCX02M  
M14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LCX02SJ  
74LCX02MTC  
MTC14  
MTC14  
74LCX02MTCX_NL  
(Note 1)  
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,  
4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: _NLpackage available in Tape and Reel only.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
An, Bn  
On  
Description  
Inputs  
Outputs  
© 2005 Fairchild Semiconductor Corporation  
ds012409  
www.fairchildsemi.com  

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