Datasheet > 74HCT280D-Q100

74HCT280D-Q100

更新时间： 2024-04-09 18:58:37

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
12页	265K
描述
9-bit odd/even parity generator/checkerProduction

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74HCT280D-Q100 数据手册

74HC280-Q100; 74HCT280-Q100

9-bit odd/even parity generator/checker

Rev. 1 — 15 January 2024

Product data sheet

1. General description

The 74HC280-Q100; 74HCT280-Q100 is a 9-bit parity generator or checker. Both even and odd

parity outputs are available. The even parity output (PE) is HIGH when an even number of data

inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs

are HIGH. Expansion to larger word sizes is accomplished by tying the even outputs (PE) of up to

nine parallel devices to the final stage data inputs. Inputs include clamp diodes. It enables the use

of current limiting resistors to interface inputs to voltages in excess of V_CC

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Word-length easily expanded by cascading

Generates either odd or even parity for nine data bits

Wide supply voltage range from 2.0 to 6.0 V

Input levels:

•

For 74HC280-Q100: CMOS level

For 74HCT280-Q100: TTL level

•

CMOS low power dissipation

High noise immunity

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Complies with JEDEC standards

•

JESD8C (2.7 V to 3.6 V)

JESD7A (2.0 V to 6.0 V)

•

ESD protection:

•

HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

3. Ordering information

Table 1. Ordering information

Type number

Temperature

range

Name

Description

Version

74HC280D-Q100

74HCT280D-Q100

-40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

12 3 4 5 6 7...12

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