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74HCT259D-Q100 PDF预览

74HCT259D-Q100

更新时间: 2024-11-21 11:11:11
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
17页 282K
描述
8-bit addressable latchProduction

74HCT259D-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.57
Is Samacsys:N其他特性:1:8 DMUX FOLLOWED BY LATCH
系列:HCTJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
逻辑集成电路类型:D LATCH湿度敏感等级:1
位数:1功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240传播延迟(tpd):57 ns
筛选级别:AEC-Q100座面最大高度:1.75 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:LOW LEVEL
宽度:3.9 mmBase Number Matches:1

74HCT259D-Q100 数据手册

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74HC259-Q100; 74HCT259-Q100  
8-bit addressable latch  
Rev. 2 — 2 September 2020  
Product data sheet  
1. General description  
The 74HC259-Q100; 74HCT259-Q100 is an 8-bit addressable latch. The device features four  
modes of operation. In the addressable latch mode, data on the D input is written into the latch  
addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed  
latches will retain their previous states. In memory mode, all latches retain their previous states and  
are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the  
addressed output follows the D input and all other outputs are LOW. In the reset mode, all outputs  
are forced LOW and unaffected by the data or address inputs. Inputs include clamp diodes. This  
enables the use of current limiting resistors to interface inputs to voltages in excess of VCC  
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
Wide supply voltage range from 2.0 V to 6.0 V  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Complies with JEDEC standards:  
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
Combined demultiplexer and 8-bit latch  
Serial-to-parallel capability  
Output from each storage bit available  
Random (addressable) data entry  
Easily expandable  
Common reset input  
Useful as a 3-to-8 active HIGH decoder  
Input levels:  
For 74HC259-Q100: CMOS level  
For 74HCT259-Q100: TTL level  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
Multiple package options  
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of  
solder joints  
 
 

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