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74HCT259D-Q100 PDF预览

74HCT259D-Q100

更新时间： 2024-11-20 12:50:43
品牌 Logo 应用领域
恩智浦 - NXP 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
20页 261K
描述
8-bit addressable latch

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中文翻译

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74HCT259D-Q100 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.58
Is Samacsys：N其他特性：1:8 DMUX FOLLOWED BY LATCH
系列：HCTJESD-30 代码：R-PDSO-G16
长度：9.9 mm逻辑集成电路类型：D LATCH
湿度敏感等级：1位数：1
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：240
传播延迟（tpd）：57 ns筛选级别：AEC-Q100
座面最大高度：1.75 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30触发器类型：LOW LEVEL
宽度：3.9 mmBase Number Matches：1

74HCT259D-Q100 数据手册

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74HC259-Q100; 74HCT259-Q100  
8-bit addressable latch  
Rev. 1 — 30 July 2012  
Product data sheet  
1. General description  
The 74HC259-Q100; 74HCT259-Q100 are high-speed Si-gate CMOS devices and are pin  
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with  
JEDEC standard No. 7A.  
The 74HC259-Q100; 74HCT259-Q100 are high-speed 8-bit addressable latches  
designed for general-purpose storage applications in digital systems. They are  
multifunctional devices capable of storing single-line data in eight addressable latches and  
providing a 3-to-8 decoder and multiplexer function with active HIGH outputs (Q0 to Q7).  
They also incorporate an active LOW common reset (MR) for resetting all latches as well  
as an active LOW enable input (LE).  
The 74HC259-Q100; 74HCT259-Q100 has four modes of operation:  
• Addressable latch mode, in this mode data on the data line (D) is written into the  
addressed latch. The addressed latch follows the data input with all non-addressed  
latches remaining in their previous states.  
• Memory mode, in this mode all latches remain in their previous states and are  
unaffected by the data or address inputs.  
• Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows  
the state of the data input (D) with all other outputs in the LOW state.  
• Reset mode, in this mode all outputs are LOW and unaffected by the address inputs  
(A0 to A2) and data input (D).  
When operating the 74HC259-Q100; 74HCT259-Q100 as an address latch, changing  
more than one address bit could impose a transient wrong address. Therefore, this should  
only be done while in the Memory mode.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Combined demultiplexer and 8-bit latch  
Serial-to-parallel capability  
Output from each storage bit available  
Random (addressable) data entry  
Easily expandable  
Common reset input  
1234567...20

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