Datasheet > 74HCT259BQ

74HCT259BQ

更新时间： 2024-11-21 11:11:19

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
18页	312K
描述
8-bit addressable latchProduction

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数据手册

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74HCT259BQ 数据手册

74HC259; 74HCT259

8-bit addressable latch

Rev. 8 — 5 December 2022

Product data sheet

1. General description

The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of

operation. In the addressable latch mode, data on the D input is written into the latch addressed

by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches

will retain their previous states. In memory mode, all latches retain their previous states and are

unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the

addressed output follows the D input and all other outputs are LOW. In the reset mode, all outputs

are forced LOW and unaffected by the data or address inputs. Inputs include clamp diodes. This

enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC

2. Features and benefits

•

Wide supply voltage range from 2.0 V to 6.0 V

•

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Complies with JEDEC standards:

•

JESD8C (2.7 V to 3.6 V)

JESD7A (2.0 V to 6.0 V)

•

Combined demultiplexer and 8-bit latch

Serial-to-parallel capability

Output from each storage bit available

Random (addressable) data entry

Easily expandable

Common reset input

Useful as a 3-to-8 active HIGH decoder

Input levels:

•

For 74HC259: CMOS level

For 74HCT259: TTL level

•

ESD protection:

•

HBM: ANSI/ESDA/Jedec JS-001 Class 2 exceeds 2000 V

CDM: ANSI/ESDA/Jedec JS-002 Class C3 exceeds 1000 V

•

Multiple package options

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

12 3 4 5 6 7...18

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