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74HCT164BQ,115 PDF预览

74HCT164BQ,115

更新时间: 2024-02-02 19:37:34
品牌 Logo 应用领域
恩智浦 - NXP PC逻辑集成电路触发器
页数 文件大小 规格书
20页 184K
描述
74HC(T)164 - 8-bit serial-in, parallel-out shift register QFN 14-Pin

74HCT164BQ,115 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFN包装说明:HVQCCN, LCC14,.1X.12,20
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.64
计数方向:RIGHT系列:HCT
JESD-30 代码:R-PQCC-N14JESD-609代码:e4
长度:3 mm逻辑集成电路类型:SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup:22000000 Hz湿度敏感等级:1
位数:8功能数量:1
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC14,.1X.12,20封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:5 V传播延迟(tpd):54 ns
认证状态:Not Qualified座面最大高度:1 mm
子类别:Shift Registers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:2.5 mm
最小 fmax:18 MHzBase Number Matches:1

74HCT164BQ,115 数据手册

 浏览型号74HCT164BQ,115的Datasheet PDF文件第2页浏览型号74HCT164BQ,115的Datasheet PDF文件第3页浏览型号74HCT164BQ,115的Datasheet PDF文件第4页浏览型号74HCT164BQ,115的Datasheet PDF文件第5页浏览型号74HCT164BQ,115的Datasheet PDF文件第6页浏览型号74HCT164BQ,115的Datasheet PDF文件第7页 
74HC164; 74HCT164  
8-bit serial-in, parallel-out shift register  
Rev. 04 — 2 February 2010  
Product data sheet  
1. General description  
The 74HC164; 74HCT164 are high-speed Si-gate CMOS devices and are pin compatible  
with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC  
standard no. 7A.  
The 74HC164; 74HCT164 are 8-bit edge-triggered shift registers with serial data entry  
and an output from each of the eight stages. Data is entered serially through one of two  
inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry  
through the other input. Both inputs must be connected together or an unused input must  
be tied HIGH.  
Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input  
and enters into Q0, which is the logical AND of the two data inputs (DSA and DSB) that  
existed one set-up time prior to the rising clock edge.  
A LOW level on the master reset (MR) input overrides all other inputs and clears the  
register asynchronously, forcing all outputs LOW.  
2. Features  
„ Input levels:  
‹ For 74HC164: CMOS level  
‹ For 74HCT164: TTL level  
„ Gated serial data inputs  
„ Asynchronous master reset  
„ Complies with JEDEC standard no. 7A  
„ ESD protection:  
‹ HBM JESD22-A114F exceeds 2000 V  
‹ MM JESD22-A115-A exceeds 200 V.  
„ Multiple package options  
„ Specified from 40 °C to +85 °C and 40 °C to +125 °C.  
 
 

74HCT164BQ,115 替代型号

型号 品牌 替代类型 描述 数据表
74AHCT594BQ,115 NXP

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