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74HCT123D,652 PDF预览

74HCT123D,652

更新时间: 2024-11-05 15:30:51
品牌 Logo 应用领域
恩智浦 - NXP 时钟输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
25页 296K
描述
74HC(T)123 - Dual retriggerable monostable multivibrator with reset SOP 16-Pin

74HCT123D,652 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOP包装说明:3.90 MM, PLASTIC, MS-012, SOT-109-1, SOP-16
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.88
其他特性:RETRIGGERABLE; TRIGGERABLE FROM CLEAR INPUT ALSO系列:HCT
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:MONOSTABLE MULTIVIBRATOR湿度敏感等级:1
数据/时钟输入次数:2功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:5 V传播延迟(tpd):77 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Prescaler/Multivibrators最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

74HCT123D,652 数据手册

 浏览型号74HCT123D,652的Datasheet PDF文件第2页浏览型号74HCT123D,652的Datasheet PDF文件第3页浏览型号74HCT123D,652的Datasheet PDF文件第4页浏览型号74HCT123D,652的Datasheet PDF文件第5页浏览型号74HCT123D,652的Datasheet PDF文件第6页浏览型号74HCT123D,652的Datasheet PDF文件第7页 
74HC123; 74HCT123  
Dual retriggerable monostable multivibrator with reset  
Rev. 8 — 16 December 2011  
Product data sheet  
1. General description  
The 74HC123; 74HCT123 are high-speed Si-gate CMOS devices and are pin compatible  
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC  
standard no. 7A.  
The 74HC123; 74HCT123 are dual retriggerable monostable multivibrators with output  
pulse width control by three methods:  
1. The basic pulse is programmed by selection of an external resistor (REXT) and  
capacitor (CEXT).  
2. Once triggered, the basic output pulse width may be extended by retriggering the  
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By  
repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made  
as long as desired. Alternatively an output delay can be terminated at any time by a  
LOW-going edge on input nRD, which also inhibits the triggering.  
3. An internal connection from nRD to the input gates makes it possible to trigger the  
circuit by a HIGH-going signal at input nRD as shown in the function table.  
Schmitt-trigger action in the nA and nB inputs, makes the circuit highly tolerant to slower  
input rise and fall times.  
The 74HC123; 74HCT123 are identical to the 74HC423; 74HCT423 but can be triggered  
via the reset input.  
2. Features and benefits  
DC triggered from active HIGH or active LOW inputs  
Retriggerable for very long pulses up to 100 % duty factor  
Direct reset terminates output pulse  
Schmitt-trigger action on all inputs except for the reset input  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from 40 C to +85 C and from 40 C to +125 C  
 
 

74HCT123D,652 替代型号

型号 品牌 替代类型 描述 数据表
74HCT123D,653 NXP

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