Datasheet > 74HCT112D-Q100

74HCT112D-Q100

更新时间： 2024-11-06 17:00:43

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
16页	266K
描述
Dual JK flip-flop with set and reset; negative-edge triggerProduction

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74HCT112D-Q100 数据手册

74HC112-Q100; 74HCT112-Q100

Dual JK flip-flop with set and reset; negative-edge trigger

Rev. 1 — 15 January 2024

Product data sheet

1. General description

The 74HC112-Q100; 74HCT112-Q100 is a dual negative-edge triggered JK flip-flop. It features

individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary

nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate

independently of the clock input. The J and K inputs control the state changes of the flip-flops as

described in the mode select function table. The J and K inputs must be stable one set-up time

prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes

that enable the use of current limiting resistors to interface inputs to voltages in excess of V_CC

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall

times.

2. Features and benefits

•

Input levels:

•

For 74HC112-Q100: CMOS level

For 74HCT112-Q100: TTL level

•

Asynchronous set and reset

Specified in compliance with JEDEC standard no. 7A

ESD protection:

•

HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

•

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74HCT112D-Q100

-40 °C to +125 °C

SO16

plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

74HC112PW-Q100 -40 °C to +125 °C

TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

12 3 4 5 6 7...16

中文翻译

下载PDF

与74HCT112D-Q100相关器件

型号	品牌	获取价格	描述	数据表
74HCT112D-T	ETC	获取价格	J-K-Type Flip-Flop
74HCT112N	NXP	获取价格	Dual JK flip-flop with set and reset; negative-edge trigger
74HCT112N,652	NXP	获取价格	74HC(T)112 - dual JK flip-flop with set and reset; negative-edge trigger DIP 16-Pin
74HCT112NB	NXP	获取价格	IC HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, F
74HCT112PW	NXP	获取价格	Dual JK flip-flop with set and reset; negative-edge trigger
74HCT112PW	NEXPERIA	获取价格	Dual JK flip-flop with set and reset; negative-edge triggerProduction
74HCT112PW,118	NXP	获取价格	74HC(T)112 - dual JK flip-flop with set and reset; negative-edge trigger TSSOP 16-Pin
74HCT112PW-T	NXP	获取价格	IC HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, P
74HCT11D	NXP	获取价格	Triple 3-input AND gate
74HCT11D	PHILIPS	获取价格	AND Gate, CMOS, PDSO14