Datasheet > 74HCT10PW

74HCT10PW

更新时间： 2024-09-14 11:11:19

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
11页	219K
描述
Triple 3-input NAND gateProduction

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数据手册

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74HCT10PW 数据手册

74HC10; 74HCT10

Triple 3-input NAND gate

Rev. 4 — 8 January 2021

Product data sheet

1. General description

The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the

use of current limiting resistors to interface inputs to voltages in excess of V_CC

2. Features and benefits

•

Complies with JEDEC standard JESD7A

Input levels:

For74HC10: CMOS level

For 74HCT10: TTL level

•

Complies with JEDEC standard no. 7A

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

•

Multiple package options

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name

Description

Version

74HC10D

-40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74HCT10D

74HC10PW

74HCT10PW

-40 °C to +125 °C

TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

4. Functional diagram

mna758

mna757

mna759

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

Fig. 3. Logic diagram (one gate)

12 3 4 5 6 7...11

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