Datasheet > 74HC74DB118

74HC74DB118

更新时间： 2024-11-11 12:31:03

品牌	Logo	应用领域
恩智浦 - NXP		触发器
页数	文件大小	规格书
21页	175K
描述
Dual D-type flip-flop with set and reset; positive edge-trigger

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数据手册

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74HC74DB118 数据手册

74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

Rev. 4 — 27 August 2012

Product data sheet

1. General description

The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have

individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary

nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time

requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at

the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to

slower clock rise and fall times. Inputs include clamp diodes that enable the use of current

limiting resistors to interface inputs to voltages in excess of V_CC

2. Features and benefits

 Input levels:

 For 74HC74: CMOS level

 For 74HCT74: TTL level

 Symmetrical output impedance

 Low power dissipation

 High noise immunity

 Balanced propagation delays

 Specified in compliance with JEDEC standard no. 7A

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Multiple package options

 Specified from 40 C to +85 C and from 40 C to +125 C

3. Ordering information

Table 1.

Type number Package

Temperature range Name

Ordering information

Description

Version

74HC74N

40 C to +125 C

DIP14

plastic dual in-line package; 14 leads (300 mil)

SOT27-1

74HCT74N

74HC74D

40 C to +125 C

SO14

plastic small outline package; 14 leads; body width

3.9 mm

SOT108-1

74HCT74D

74HC74DB

74HCT74DB

SSOP14

plastic shrink small outline package; 14 leads; body SOT337-1

width 5.3 mm

12 3 4 5 6 7...21

中文翻译

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与74HC74DB118相关器件

型号	品牌	获取价格	描述	数据表
74HC74DG	ONSEMI	获取价格	Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
74HC74D-Q100	NEXPERIA	获取价格	Dual D-type flip-flop with set and reset; positive edge-trigger
74HC74DR2	ONSEMI	获取价格	Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
74HC74DR2G	ONSEMI	获取价格	Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
74HC74D-T	NXP	获取价格	Dual D-type flip-flop with set and reset; positive-edge trigger
74HC74DTR2	ONSEMI	获取价格	Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
74HC74DTR2G	ONSEMI	获取价格	Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
74HC74N	NXP	获取价格	Dual D-type flip-flop with set and reset; positive-edge trigger
74HC74N,652	NXP	获取价格	74HC74N
74HC74N652	NXP	获取价格	Dual D-type flip-flop with set and reset; positive edge-trigger