是否Rohs认证: | 符合 | 生命周期: | Transferred |
零件包装代码: | SOIC | 包装说明: | 3.90 MM, PLASTIC, MS-012, SOT-108-1, SO-14 |
针数: | 14 | Reach Compliance Code: | compliant |
HTS代码: | 8542.39.00.01 | 风险等级: | 3.39 |
系列: | HC/UH | JESD-30 代码: | R-PDSO-G14 |
长度: | 8.65 mm | 负载电容(CL): | 50 pF |
逻辑集成电路类型: | D FLIP-FLOP | 最大频率@ Nom-Sup: | 20000000 Hz |
最大I(ol): | 0.004 A | 湿度敏感等级: | 1 |
位数: | 1 | 功能数量: | 2 |
端子数量: | 14 | 最高工作温度: | 125 °C |
最低工作温度: | -40 °C | 输出极性: | COMPLEMENTARY |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | SOP |
封装等效代码: | SOP14,.25 | 封装形状: | RECTANGULAR |
封装形式: | SMALL OUTLINE | 包装方法: | TUBE |
峰值回流温度(摄氏度): | 260 | 电源: | 2/6 V |
传播延迟(tpd): | 265 ns | 认证状态: | Not Qualified |
座面最大高度: | 1.75 mm | 子类别: | FF/Latches |
最大供电电压 (Vsup): | 6 V | 最小供电电压 (Vsup): | 2 V |
标称供电电压 (Vsup): | 5 V | 表面贴装: | YES |
技术: | CMOS | 温度等级: | AUTOMOTIVE |
端子面层: | NICKEL/PALLADIUM/GOLD (NI/PD/AU) | 端子形式: | GULL WING |
端子节距: | 1.27 mm | 端子位置: | DUAL |
处于峰值回流温度下的最长时间: | 30 | 触发器类型: | POSITIVE EDGE |
宽度: | 3.9 mm | 最小 fmax: | 24 MHz |
Base Number Matches: | 1 |
型号 | 品牌 | 替代类型 | 描述 | 数据表 |
74HC74D,653 | NXP |
类似代替 |
74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger SOIC 14-Pin | |
74HC74N,652 | NXP |
类似代替 |
74HC74N | |
MC74HC74ADR2G | ONSEMI |
功能相似 |
Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
74HC74D,653 | NXP |
获取价格 |
74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger SOIC 14-Pin | |
74HC74D/G,118 | NXP |
获取价格 |
74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger SOIC 14-Pin | |
74HC74D/T3 | NXP |
获取价格 |
IC HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 3 | |
74HC74DB | NXP |
获取价格 |
Dual D-type flip-flop with set and reset; positive-edge trigger | |
74HC74DB118 | NXP |
获取价格 |
Dual D-type flip-flop with set and reset; positive edge-trigger | |
74HC74DG | ONSEMI |
获取价格 |
Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS | |
74HC74D-Q100 | NEXPERIA |
获取价格 |
Dual D-type flip-flop with set and reset; positive edge-trigger | |
74HC74DR2 | ONSEMI |
获取价格 |
Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS | |
74HC74DR2G | ONSEMI |
获取价格 |
Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS | |
74HC74D-T | NXP |
获取价格 |
Dual D-type flip-flop with set and reset; positive-edge trigger |