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74HC73 PDF预览

74HC73

更新时间: 2024-11-10 22:53:15
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
21页 108K
描述
Dual JK flip-flop with reset; negative-edge trigger

74HC73 数据手册

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74HC73  
Dual JK flip-flop with reset; negative-edge trigger  
Rev. 03 — 12 November 2004  
Product data sheet  
1. General description  
The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power  
Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC  
standard no. 7A.  
The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock  
(nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.  
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock  
transition for predictable operation.  
The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock  
and data inputs, forcing the nQ output LOW and the nQ output HIGH.  
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock  
rise and fall times.  
2. Features  
Low-power dissipation  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
Multiple package options  
Specified from 40 °C to +80 °C and from 40 °C to +125 °C.  

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