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74HC4053DB,118 PDF预览

74HC4053DB,118

更新时间: 2024-01-22 06:48:54
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
33页 164K
描述
74HC(T)4053 - Triple 2-channel analog multiplexer/demultiplexer SSOP1 16-Pin

74HC4053DB,118 技术参数

是否Rohs认证:符合生命周期:Transferred
零件包装代码:SSOP1包装说明:SSOP, SSOP16,.3
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.34
Is Samacsys:N模拟集成电路 - 其他类型:SPDT
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:6.2 mm湿度敏感等级:1
信道数量:1功能数量:3
端子数量:16标称断态隔离度:50 dB
通态电阻匹配规范:8 Ω最大通态电阻 (Ron):160 Ω
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP16,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2/10 V认证状态:Not Qualified
座面最大高度:2 mm最大信号电流:0.025 A
子类别:Multiplexer or Switches最大供电电流 (Isup):0.32 mA
最大供电电压 (Vsup):10 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
最长断开时间:36 ns最长接通时间:37 ns
切换:BREAK-BEFORE-MAKE技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:5.3 mmBase Number Matches:1

74HC4053DB,118 数据手册

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74HC4053; 74HCT4053  
Triple 2-channel analog multiplexer/demultiplexer  
Rev. 04 — 9 May 2006  
Product data sheet  
1. General description  
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible  
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A.  
The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a  
common enable input (E). Each multiplexer/demultiplexer has two independent  
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select  
inputs (Sn).  
With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to S3.  
With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3.  
VCC and GND are the supply voltage pins for the digital control inputs (S1 to S3 and E).  
The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for  
74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between VCC  
as a positive limit and VEE as a negative limit. VCC VEE may not exceed 10.0 V.  
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically  
ground).  
2. Features  
Low ON resistance:  
80 (typical) at VCC VEE = 4.5 V  
70 (typical) at VCC VEE = 6.0 V  
60 (typical) at VCC VEE = 9.0 V  
Logic level translation:  
To enable 5 V logic to communicate with ±5 V analog signals  
Typical ‘break before make’ built in  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM EIA/JESD22-A114-C exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
 
 

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