Datasheet > 74HC4053BQ-Q100

74HC4053BQ-Q100

更新时间： 2024-02-02 14:14:24

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
30页	320K
描述
Triple 2-channel analog multiplexer/demultiplexer

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技术参数
数据手册

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74HC4053BQ-Q100 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.6	JESD-609代码：	e4
湿度敏感等级：	1	峰值回流温度（摄氏度）：	260
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	处于峰值回流温度下的最长时间：	30
Base Number Matches：	1

74HC4053BQ-Q100 数据手册

74HC4053-Q100; 74HCT4053-Q100

Triple 2-channel analog multiplexer/demultiplexer

Rev. 2 — 22 November 2012

Product data sheet

1. General description

The 74HC4053-Q100; 74HCT4053-Q100 is a high-speed Si-gate CMOS device and is pin

compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with

JEDEC standard no. 7A.

The 74HC4053-Q100; 74HCT4053-Q100 is triple 2-channel analog

multiplexer/demultiplexer with a common enable input (E). Each multiplexer/demultiplexer

has two independent inputs/outputs (nY0 and nY1), a common input/output (nZ) and three

digital select inputs (Sn). With E LOW, one of the two switches is selected

(low-impedance ON-state) by S1 to S3. With E HIGH, all switches are in the

high-impedance OFF-state, independent of S1 to S3.

V_CCand GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).

The V_CCto GND ranges are 2.0 V to 10.0 V for 74HC4053-Q100, and 4.5 V to 5.5 V for

74HCT4053-Q100. The analog inputs/outputs (nY0 to nY1, and nZ) can swing between

_CCas a positive limit and V_EEas a negative limit. V_CC V_EEmay not exceed 10.0 V.

For operation as a digital multiplexer/demultiplexer, V_EEis connected to GND (typically

ground).

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Wide analog input voltage range from 5 V to +5 V

 Low ON resistance:

 80  (typical) at V_CC V_EE= 4.5 V

 70  (typical) at V_CC V_EE= 6.0 V

 60  (typical) at V_CC V_EE= 9.0 V

 Logic level translation: to enable 5 V logic to communicate with 5 V analog signals

 Typical ‘break before make’ built-in

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 CDM AEC-Q100-011 revision B exceeds 1000 V

 Multiple package options

12 3 4 5 6 7...30

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