Datasheet > 74HC2G32DP

74HC2G32DP

更新时间： 2024-09-15 14:54:19

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
11页	222K
描述
Dual 2-input OR gateProduction

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74HC2G32DP 数据手册

74HC2G32; 74HCT2G32

Dual 2-input OR gate

Rev. 7 — 17 November 2023

Product data sheet

1. General description

The 74HC2G32; 74HCT2G32 is a dual 2-input OR gate. Inputs include clamp diodes. This enables

the use of current limiting resistors to interface inputs to voltages in excess of V_CC

2. Features and benefits

•

Wide supply voltage range from 2.0 V to 6.0 V

Input levels:

For 74HC2G32: CMOS level

For 74HCT2G32: TTL level

•

CMOS low power dissipation

High noise immunity

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Complies with JEDEC standard: JESD7A (2.0 V to 6.0 V)

ESD protection:

•

HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

•

Specified from -40 °C to +85 °C and -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74HC2G32DP

74HCT2G32DP

-40 °C to +125 °C

TSSOP8

plastic thin shrink small outline package; 8 leads; SOT505-2

body width 3 mm; lead length 0.5 mm

74HC2G32DC

74HCT2G32DC

-40 °C to +125 °C

VSSOP8

plastic very thin shrink small outline package;

8 leads; body width 2.3 mm

SOT765-1

4. Marking

Table 2. Marking code

Type number

Marking code [1]

74HC2G32DP

74HCT2G32DP

74HC2G32DC

74HCT2G32DC

H32

T32

H32

T32

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

12 3 4 5 6 7...11

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