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74HC259D PDF预览

74HC259D

更新时间: 2023-12-20 18:44:37
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
11页 233K
描述
Octal 8-bit Addressable Latch, SOIC16

74HC259D 数据手册

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74HC259D  
CMOS Digital Integrated Circuits Silicon Monolithic  
74HC259D  
1. Functional Description  
8-Bit Addressable Latch  
2. General  
The 74HC259D is a high speed CMOS ADDRESSABLE LATCH fabricated with silicon gate C2MOS technology.  
It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power  
dissipation.  
The respective bits are controlled by address inputs A, B, and C. When CLEAR input is held high and enable  
input G is held low, the data is written into the bit selected by address inputs, the other bit hold their previous  
conditions.  
When both CLEAR and G held high, writing of all bits is inhibited regardless of adress inputs, and their previous  
condition are held. When CLEAR is held low and G is held high, all bits are resent to low regardless of the other  
inputs. When both of CLEAR and G held low, all bits which isn't selected by adress inputs are resent to low.  
All inputs are equipped with protection circuits against static discharge or transient excess voltage.  
3. Features  
(1) High speed: tpd = 15 ns (typ.) at VCC = 5 V  
(2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25  
(3) Balanced propagation delays: tPLH tPHL  
(4) Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V  
4. Packaging  
SOIC16  
Start of commercial production  
2016-05  
©2016 Toshiba Corporation  
2016-08-04  
Rev.3.0  
1

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