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74HC244D/T3 PDF预览

74HC244D/T3

更新时间: 2024-11-20 15:26:35
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
22页 128K
描述
IC HC/UH SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT-163-1, SOP-20, Bus Driver/Transceiver

74HC244D/T3 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.02系列:HC/UH
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:12.8 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):165 ns认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmBase Number Matches:1

74HC244D/T3 数据手册

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74HC244; 74HCT244  
Octal buffer/line driver; 3-state  
Rev. 03 — 22 December 2005  
Product data sheet  
1. General description  
The 74HC244; 74HCT244 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL (LSTTL).  
The 74HC244; 74HCT244 has octal non-inverting buffer/line drivers with 3-state outputs.  
The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on  
nOE causes the outputs to assume a high-impedance OFF-state. The 74HC244;  
74HCT244 is identical to the 74HC240; 74HCT240 but has non-inverting outputs.  
2. Features  
Octal bus interface  
Non-inverting 3-state outputs  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM EIA/JESD22-A114-C exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
3. Quick reference data  
Table 1:  
Quick reference data  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
Symbol Parameter  
74HC244  
Conditions  
Min  
Typ  
Max  
Unit  
tPHL  
tPLH  
,
propagation delay  
nAn to nYn  
VCC = 5 V; CL = 15 pF  
-
9
-
ns  
Ci  
input capacitance  
-
-
3.5  
35  
-
-
pF  
pF  
[1]  
CPD  
power dissipation  
capacitance  
per buffer; VI = GND to  
VCC  
74HCT244  
tPHL  
tPLH  
,
propagation delay  
nAn to nYn  
VCC = 5 V; CL = 15 pF  
-
11  
-
ns  
Ci  
input capacitance  
-
-
3.5  
35  
-
-
pF  
pF  
[1]  
CPD  
power dissipation  
capacitance  
per buffer; VI = GND to  
(VCC 1.5 V)  
[1] CPD is used to determine the dynamic power dissipation (PD in µW):  
PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where:  

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