5秒后页面跳转
74HC191D PDF预览

74HC191D

更新时间: 2023-09-03 20:30:40
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
18页 291K
描述
Presettable synchronous 4-bit binary up/down counterProduction

74HC191D 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:1.16其他特性:TCO OUTPUT
计数方向:BIDIRECTIONAL系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm负载电容(CL):50 pF
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
工作模式:SYNCHRONOUS湿度敏感等级:1
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):66 ns认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:13 MHzBase Number Matches:1

74HC191D 数据手册

 浏览型号74HC191D的Datasheet PDF文件第2页浏览型号74HC191D的Datasheet PDF文件第3页浏览型号74HC191D的Datasheet PDF文件第4页浏览型号74HC191D的Datasheet PDF文件第5页浏览型号74HC191D的Datasheet PDF文件第6页浏览型号74HC191D的Datasheet PDF文件第7页 
74HC191  
Presettable synchronous 4-bit binary up/down counter  
Rev. 6 — 8 September 2021  
Product data sheet  
1. General description  
The 74HC191 is an asynchronously presettable 4-bit binary up/down counter. It contains four  
master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and  
synchronous count-up and count-down operation. Asynchronous parallel load capability permits  
the counter to be preset to any desired value. Information present on the parallel data inputs (D0  
to D3) is loaded into the counter and appears on the outputs when the parallel load (PL) input is  
LOW. This operation overrides the counting function. Counting is inhibited by a HIGH level on the  
count enable (CE) input. When CE is LOW internal state changes are initiated synchronously by  
the LOW-to-HIGH transition of the clock input. The up/down (U/D) input signal determines the  
direction of counting as indicated in the function table. The CE input may go LOW when the clock is  
in either state, however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH.  
Also, the U/D input should be changed only when either CE or CP is HIGH. Overflow/underflow  
indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC).  
The TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down  
mode or reaches '15' in the count-up-mode. The TC output will remain HIGH until a state change  
occurs, either by counting or presetting, or until U/D is changed. Do not use the TC output as a  
clock signal because it is subject to decoding spikes. The TC signal is used internally to enable  
the RC output. When TC is HIGH and CE is LOW, the RC output follows the clock pulse (CP). This  
feature simplifies the design of multistage counters as shown in Fig. 5 and Fig. 6. In Fig. 5, each  
RC output is used as the clock input to the next higher stage. It is only necessary to inhibit the  
first stage to prevent counting in all stages, since a HIGH on CE inhibits the RC output pulse. The  
timing skew between state changes in the first and last stages is represented by the cumulative  
delay of the clock as it ripples through the preceding stages. This can be a disadvantage of this  
configuration in some applications. Fig. 6 shows a method of causing state changes to occur  
simultaneously in all stages. The RC outputs propagate the carry/borrow signals in ripple fashion  
and all clock inputs are driven in parallel. In this configuration the duration of the clock LOW state  
must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through  
to the last stage before the clock goes HIGH. Since the RC output of any package goes HIGH  
shortly after its CP input goes HIGH there is no such restriction on the HIGH-state duration of the  
clock. In Fig. 7, the configuration shown avoids ripple delays and their associated restrictions.  
Combining the TC signals from all the preceding stages forms the CE input for a given stage. An  
enable must be included in each carry gate in order to inhibit counting. The TC output of a given  
stage it not affected by its own CE signal therefore the simple inhibit scheme of Fig. 5 and Fig. 6  
does not apply. Inputs include clamp diodes. This enables the use of current limiting resistors to  
interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Wide supply voltage range from 2.0 to 6.0 V  
CMOS low power dissipation  
High noise immunity  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
CMOS input levels  
Synchronous reversible counting  
Asynchronous parallel load  
Count enable control for synchronous expansion  
Single up/down control input  
 
 

74HC191D 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC191M TI

功能相似

SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SN74HC191D TI

功能相似

4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

与74HC191D相关器件

型号 品牌 获取价格 描述 数据表
74HC191DB NXP

获取价格

Presettable synchronous 4-bit binary up/down counter
74HC191DB,112 NXP

获取价格

74HC(T)191 - Presettable synchronous 4-bit binary up/down counter SSOP1 16-Pin
74HC191DB,118 NXP

获取价格

74HC(T)191 - Presettable synchronous 4-bit binary up/down counter SSOP1 16-Pin
74HC191DB-T NXP

获取价格

IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, S
74HC191D-T ETC

获取价格

Synchronous Up/Down Counter
74HC191N NXP

获取价格

Presettable synchronous 4-bit binary up/down counter
74HC191N,652 NXP

获取价格

74HC(T)191 - Presettable synchronous 4-bit binary up/down counter DIP 16-Pin
74HC191N-B PHILIPS

获取价格

Binary Counter, Synchronous, Bidirectional, CMOS, PDIP16
74HC191PW NXP

获取价格

Presettable synchronous 4-bit binary up/down counter
74HC191PW NEXPERIA

获取价格

Presettable synchronous 4-bit binary up/down counterProduction