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74HC132 PDF预览

74HC132

更新时间: 2024-09-13 08:03:39
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
9页 135K
描述
Quad 2−Input NAND Gate with Schmitt−Trigger Inputs High−Performance Silicon−Gate CMOS

74HC132 数据手册

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74HC132  
Quad 2−Input NAND Gate  
with Schmitt−Trigger Inputs  
HighPerformance SiliconGate CMOS  
The 74HC132 is identical in pinout to the LS132. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
http://onsemi.com  
The HC132 can be used to enhance noise immunity or to square up  
slowly changing waveforms.  
MARKING  
DIAGRAMS  
Features  
14  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 mA  
SOIC14  
D SUFFIX  
CASE 751A  
HC132G  
AWLYWW  
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements as Defined by JEDEC  
Standard No. 7A  
ESD Performance: HBM > 2000 V; Machine Model > 200 V  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
These are PbFree Devices  
14  
1
HC  
132  
TSSOP14  
DT SUFFIX  
CASE 948G  
ALYW G  
G
HC132 = Device Code  
A
= Assembly Location  
L, WL = Wafer Lot  
= Year  
A1  
B1  
1
2
14  
13 B4  
12  
V
CC  
Y
W, WW = Work Week  
Y1  
A2  
3
4
A4  
G or G = PbFree Package  
11 Y4  
10 B3  
(Note: Microdot may be in either location)  
B2  
Y2  
5
6
9
8
A3  
Y3  
GND  
7
FUNCTION TABLE  
Inputs  
Output  
Y
Figure 1. Pin Assignment  
A
B
L
L
H
H
L
H
L
H
H
H
L
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
March, 2007 Rev. 1  
74HC132/D  

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