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74HC125D PDF预览

74HC125D

更新时间: 2024-11-05 14:54:23
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
8页 192K
描述
Quad Buffer, SOIC14

74HC125D 数据手册

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74HC125D,74HC126D  
CMOS Digital Integrated Circuits Silicon Monolithic  
74HC125D,74HC126D  
1. Functional Description  
Quad Bus Buffer, Non-Inverted 3-State Outputs  
74HC125D: Quad Bus Buffer  
74HC126D: Quad Bus Buffer  
2. General  
The 74HC125D,74HC126D are high speed CMOS QUAD BUS BUFFERs fabricated with silicon gate C2MOS  
technology.  
They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power  
dissipation.  
The 74HC125D requires the 3-state control input G to be set high to place the output into the high impedance  
state, whereas the 74HC126D requires the control input to be set low to place the output into high impedance.  
All inputs are equipped with protection circuits against static discharge or transient excess voltage.  
3. Features  
(1) High speed: tpd = 10 ns (typ.) at VCC = 6.0 V  
(2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25  
(3) Balanced propagation delays: tPLH tPHL  
(4) Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V  
4. Packaging  
SOIC14  
Start of commercial production  
2016-02  
©2016 Toshiba Corporation  
2016-08-04  
Rev.4.0  
1

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