Datasheet > 逻辑 > 栅极> 74HC11PW

74HC11PW

更新时间： 2024-11-16 06:31:51

品牌	Logo	应用领域
恩智浦 - NXP		逻辑集成电路光电二极管
页数	文件大小	规格书
15页	251K
描述
Triple 3-input AND gate

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数据手册

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74HC11PW 数据手册

74HC11; 74HCT11

Triple 3-input AND gate

Rev. 04 — 25 March 2010

Product data sheet

1. General description

The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC

standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).

The 74HC11; 74HCT11 provides a triple 3-input AND function.

2. Features

Input levels:

For 74HC11: CMOS level

For 74HCT11: TTL level

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Multiple package options

Specified from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

Table 1.

Type number Package

Temperature range Name

Ordering information

Description

Version

74HC11N

−40 °C to +125 °C

DIP14

plastic dual in-line package; 14 leads (300 mil)

SOT27-1

74HCT11N

74HC11D

SO14

plastic small outline package; 14 leads; body width

3.9 mm

SOT108-1

74HCT11D

74HC11DB

74HCT11DB

74HC11PW

74HCT11PW

SSOP14

TSSOP14

plastic shrink small outline package; 14 leads; body SOT337-1

width 5.3 mm

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

12 3 4 5 6 7...15

中文翻译

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74HC11PW-T	NXP	获取价格	暂无描述
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