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74HC10D PDF预览

74HC10D

更新时间: 2024-11-17 11:11:19
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
11页 219K
描述
Triple 3-input NAND gateProduction

74HC10D 数据手册

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74HC10; 74HCT10  
Triple 3-input NAND gate  
Rev. 4 — 8 January 2021  
Product data sheet  
1. General description  
The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the  
use of current limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Complies with JEDEC standard JESD7A  
Input levels:  
For74HC10: CMOS level  
For 74HCT10: TTL level  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number Package  
Temperature range Name  
Description  
Version  
74HC10D  
-40 °C to +125 °C  
SO14  
plastic small outline package; 14 leads;  
body width 3.9 mm  
SOT108-1  
74HCT10D  
74HC10PW  
74HCT10PW  
-40 °C to +125 °C  
TSSOP14 plastic thin shrink small outline package; 14 leads;  
body width 4.4 mm  
SOT402-1  
4. Functional diagram  
1
&
&
12  
6
2
1
2
1A  
1B  
1C  
2A  
2B  
2C  
3A  
3B  
3C  
1Y  
2Y  
13  
12  
6
13  
3
3
4
5
4
5
A
B
C
9
9
10  
11  
3Y  
8
10  
11  
&
Y
8
mna758  
mna757  
mna759  
Fig. 1. Logic symbol  
Fig. 2. IEC logic symbol  
Fig. 3. Logic diagram (one gate)  
 
 
 
 

74HC10D 替代型号

型号 品牌 替代类型 描述 数据表
74HC10D,653 NXP

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