Datasheet > 74HC107-Q100

74HC107-Q100

更新时间： 2024-11-17 01:18:47

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
17页	747K
描述
Dual JK flip-flop with reset; negative-edge trigger

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74HC107-Q100 数据手册

74HC107-Q100; 74HCT107-Q100

Dual JK flip-flop with reset; negative-edge trigger

Rev. 2 — 26 January 2015

Product data sheet

1. General description

The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop

featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q

and Q outputs. The reset is an asynchronous active LOW input and operates

independently of the clock input. The J and K inputs control the state changes of the

flip-flops as described in the mode select function table. The J and K inputs must be stable

one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs

include clamp diodes that enable the use of current limiting resistors to interface inputs to

voltages in excess of V_CC

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Input levels:

 For 74HC107-Q100: CMOS level

 For 74HCT107-Q100: TTL level

 Complies with JEDEC standard no. 7A

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74HC107D-Q100

74HCT107D-Q100

74HC107PW-Q100

40 C to +125 C

SO14

plastic small outline package; 14 leads; body width SOT108-1

3.9 mm

40 C to +125 C

TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1

body width 4.4 mm

12 3 4 5 6 7...17

中文翻译

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