生命周期: | Active | 包装说明: | , |
Reach Compliance Code: | unknown | 风险等级: | 5.78 |
逻辑集成电路类型: | AND-OR/AND-OR-INVERT GATE | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
74H62PC | FAIRCHILD |
获取价格 |
Gate, TTL, PDIP14, | |
74H62PCQM | FAIRCHILD |
获取价格 |
Gate, TTL, PDIP14, | |
74H71A | NXP |
获取价格 |
IC TTL/H/L SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, FF | |
74H71F | NXP |
获取价格 |
TTL/H/L SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 | |
74H71FC | FAIRCHILD |
获取价格 |
J-K Flip-Flop, 1-Func, Master-slave Triggered, TTL, CDFP14, | |
74H71FCQM | FAIRCHILD |
获取价格 |
J-K Flip-Flop, 1-Func, Master-slave Triggered, TTL, CDFP14, | |
74H71FCQR | FAIRCHILD |
获取价格 |
J-K Flip-Flop, 1-Func, Master-slave Triggered, TTL, CDFP14, | |
74H71PCQM | FAIRCHILD |
获取价格 |
J-K Flip-Flop, 1-Func, Master-slave Triggered, TTL, PDIP14, | |
74H72A | NXP |
获取价格 |
IC TTL/H/L SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, DI | |
74H72DC | FAIRCHILD |
获取价格 |
Jbar-Kbar Flip-Flop, 1-Func, Master-slave Triggered, TTL, CDIP14, |