生命周期: | Obsolete | 包装说明: | , |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.65 | 系列: | TTL/H/L |
JESD-30 代码: | R-GDIP-T14 | 逻辑集成电路类型: | AND-OR/AND-OR-INVERT GATE |
功能数量: | 1 | 输入次数: | 10 |
端子数量: | 14 | 最高工作温度: | 70 °C |
最低工作温度: | 输出特性: | OPEN-COLLECTOR | |
封装主体材料: | CERAMIC, GLASS-SEALED | 封装形状: | RECTANGULAR |
封装形式: | IN-LINE | 最大电源电流(ICC): | 9 mA |
认证状态: | Not Qualified | 标称供电电压 (Vsup): | 5 V |
表面贴装: | NO | 技术: | TTL |
温度等级: | COMMERCIAL | 端子形式: | THROUGH-HOLE |
端子位置: | DUAL | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
74H62FC | FAIRCHILD |
获取价格 |
Gate, TTL, CDFP14, | |
74H62FCQM | FAIRCHILD |
获取价格 |
Gate, TTL, CDFP14, | |
74H62N | ROCHESTER |
获取价格 |
AND-OR/AND-OR-Invert Gate | |
74H62PC | FAIRCHILD |
获取价格 |
Gate, TTL, PDIP14, | |
74H62PCQM | FAIRCHILD |
获取价格 |
Gate, TTL, PDIP14, | |
74H71A | NXP |
获取价格 |
IC TTL/H/L SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, FF | |
74H71F | NXP |
获取价格 |
TTL/H/L SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 | |
74H71FC | FAIRCHILD |
获取价格 |
J-K Flip-Flop, 1-Func, Master-slave Triggered, TTL, CDFP14, | |
74H71FCQM | FAIRCHILD |
获取价格 |
J-K Flip-Flop, 1-Func, Master-slave Triggered, TTL, CDFP14, | |
74H71FCQR | FAIRCHILD |
获取价格 |
J-K Flip-Flop, 1-Func, Master-slave Triggered, TTL, CDFP14, |