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74FST3345DW PDF预览

74FST3345DW

更新时间: 2024-09-15 21:55:31
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器开关逻辑集成电路光电二极管
页数 文件大小 规格书
6页 91K
描述
8-Bit Bus Switch

74FST3345DW 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-20
针数:20Reach Compliance Code:not_compliant
Factory Lead Time:1 week风险等级:5.18
Is Samacsys:N系列:CBT/FST/QS/5C/B
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:5 V传播延迟(tpd):0.25 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

74FST3345DW 数据手册

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74FST3345  
8−Bit Bus Switch  
The ON Semiconductor 74FST3345 is an 8−bit, high performance  
switch. The device is CMOS TTL compatible when operating between  
4 and 5.5 Volts. The device exhibits extremely low R  
and adds  
ON  
nearly zero propagation delay. The device adds no noise or ground  
bounce to the system.  
The device consists of an 8−bit switch with two Output/Enable pins  
(OE and OE).  
http://onsemi.com  
MARKING  
DIAGRAMS  
20  
Features  
20  
R t 4 W Typical  
ON  
Less Than 0.25 ns−Max Delay Through Switch  
Nearly Zero Standby Current  
No Circuit Bounce  
Control Inputs are TTL/CMOS Compatible  
Pin−For−Pin Compatible with QS3345, FST3345, CBT3345  
All Popular Packages: QSOP−20, TSSOP−20, SOIC−20  
All Devices in Package TSSOP are Inherently Pb−Free*  
1
FST3345  
AWLYYWW  
SOIC−20  
DW SUFFIX  
CASE 751D  
1
20  
20  
1
FST  
3345  
ALYW  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
V
CC  
OE  
TSSOP−20  
DT SUFFIX  
CASE 948E  
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
1
20  
20  
FST3345  
AWLYWW  
1
GND  
QSOP−20  
QS SUFFIX  
CASE 492A  
1
Figure 1. 20−Lead Pinout  
2
9
18  
A
A
B
B
0
0
A
= Assembly Location  
= Year  
L, WL = Wafer Lot  
Y
W, WW = Work Week  
11  
7
7
PIN NAMES  
Pin  
1
OE  
OE  
Description  
19  
OE , OE  
Bus Switch Enables  
1
2
Figure 2. Logic Diagram  
1A, 2A  
1B, 2B  
Bus A  
Bus B  
TRUTH TABLE  
Inputs  
Function  
OE  
X
OE  
L
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
Connect  
Connect  
H
X
L
H
Disconnect  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
January, 2005 − Rev. 1  
74FST3345/D  

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