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74FCT162500CTPVCT PDF预览

74FCT162500CTPVCT

更新时间： 2024-11-25 22:49:47
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德州仪器 - TI /
页数 文件大小 规格书
6页 66K
描述
18-Bit Registered Transceivers

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74FCT162500CTPVCT 数据手册

 浏览型号74FCT162500CTPVCT的Datasheet PDF文件第2页浏览型号74FCT162500CTPVCT的Datasheet PDF文件第3页浏览型号74FCT162500CTPVCT的Datasheet PDF文件第4页浏览型号74FCT162500CTPVCT的Datasheet PDF文件第5页浏览型号74FCT162500CTPVCT的Datasheet PDF文件第6页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT16500T  
CY74FCT162500T  
SCCS056 - August 1994 - Revised March 2000  
18-Bit Registered Transceivers  
Features  
Functional Description  
• FCT-C speed at 4.6 ns  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Typical output skew < 250 ps  
• ESD > 2000V  
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)  
packages  
• Industrial temperature range of −40˚C to +85˚C  
• VCC = 5V ± 10%  
These 18-bit universal bus transceivers can be operated in  
transparent, latched, or clock modes by combining D-type  
latches and D-type flip-flops. Data flow in each direction is  
controlled by output-enable (OEAB and OEBA), latch enable  
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA)  
inputs. For A-to-B data flow, the device operates in transparent  
mode when LEAB is HIGH. When LEAB is LOW, the A data is  
latched if CLKAB is held at a HIGH or LOW logic level. If LEAB  
is LOW, the A bus data is stored in the latch/flip-flop on the  
HIGH-to-LOW transition of CLKAB. OEAB performs the output  
enable function on the B port. Data flow from B-to-A is similar  
to that of A-to-B and is controlled by OEBA, LEBA, and  
CLKBA. The output buffers are designed with power-off  
disable feature that allows live insertion of boards.  
CY74FCT16500T Features:  
• 64 mA sink current, 32 mA source current  
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,  
TA = 25˚C  
The CY74FCT16500T is ideally suited for driving  
high-capacitance loads and low-impedance backplanes.  
The CY74FCT162500T has 24-mA balanced output drivers  
with current limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce. The  
CY74FCT162500T is ideal for driving transmission lines.  
CY74FCT162500T Features:  
• Balanced 24 mA output drivers  
• Reduced system switching noise  
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,  
TA= 25˚C  
Logic Block Diagram  
Pin Configuration  
SSOP/TSSOP  
Top View  
GND  
1
2
3
4
56  
55  
54  
OEAB  
LEAB  
CLKAB  
B
1
A
1
OEAB  
GND  
GND  
53  
52  
51  
50  
B
2
A
2
5
6
CLKBA  
B
V
A
3
3
V
CC  
CC  
LEBA  
OEBA  
7
B
A
4
4
5
6
49  
48  
47  
46  
8
A
A
B
B
5
6
9
CLKAB  
LEAB  
10  
11  
GND  
GND  
A
7
B
7
45  
44  
43  
12  
13  
A
A
B
B
B
8
9
8
C
D
C
D
14  
15  
16  
17  
18  
9
B
1
A
10  
42  
41  
A
1
10  
A
A
B
11  
B
12  
11  
12  
40  
39  
38  
GND  
GND  
C
D
C
D
A
A
A
B
13  
14  
15  
19  
20  
21  
22  
23  
13  
14  
15  
B
37  
36  
35  
34  
B
V
V
CC  
CC  
B
16  
A
16  
17  
A
33  
32  
31  
30  
29  
B
17  
24  
25  
TO 17 OTHER CHANNELS  
GND  
GND  
FCT16500-1  
A
B
18  
26  
27  
28  
18  
OEBA  
LEBA  
CLKBA  
GND  
FCT16500-2  
Copyright © 2000, Texas Instruments Incorporated  
123456

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74FCT162500CTPVCT 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT16500BDLR TI

完全替代

 18-bit universal bus transceivers with 3-state outputs 56-SSOP -40 to 85
SN74ABT16500BDL TI

完全替代

 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT162500DL TI

完全替代

 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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